Current mobile platforms, such as mobile phones contain NOR, NAND and DRAM type of memory. Each of these memories has a different use and different read/write timing cycles. DRAM is fastest of NOR, NAND, and DRAM memories and has the characteristics of symmetrical read/write performance. The bus delay (i.e. the time to transfer data from a host buffer to a memory buffer) is very short for all the memories. The internal memory delay (i.e. the time to transfer data from the memory buffer to a memory array) is very short for DRAM, but relatively large for NAND and NOR type memory. A dram at 166 MHz, for example, could achieve a bandwidth in a range of about 2 GB/sec. However, NOR and NAND type memories could achieve a bandwidth in the range of about 10 MB/sec to about 100 MB/sec.
Buffers for each type of memory are specifically designated to each specific type of memory. In most cases, not all of the memories are accessed at the same time by an application. Therefore, the buffers specifically dedicated to each type of these memories are either empty or completely full at various times depending on load conditions. Having many separate memories increases the complexity and the cost of a system. For example, there may be times when an optical decoder is not being used because no image is being displayed or captures. During those times, the memory dedicated to the optic decoder will be unused even though it may be useful for other subsystems. Because all of the buffers in the system are not available to all of the subsystems that require temporary storage, the resources will be underutilized, and consequently the system will be less efficient than it could be. Sometimes, data in one memory has to be transferred to another memory in order to be processed or shared with the processor attached to a second memory. Hence, the system is less efficient because of the extra transfer operations required to share data. Because the buffers are dedicated to each memory and often reside empty, there is a need to utilize these resources in order to improve read/write performance and reduce latency, in particular for telecommunications.
In response to inexorable demand for faster data throughput and larger storage capacity, memory systems have progressed from asynchronous to synchronous designs. As systems progress to accommodate more memory devices than before each additional memory device connection reduces signaling margins due to increased bus capacitance and number of stubs and therefore, increasingly compromising the peak transfer rate of the system. Designers often make a choice between system capacity and data throughput. Hence, one such trend arising is an ongoing effort to connect memories in chain architecture while allocating adequate bus ownership for efficient transfers.
Systems often have shared resources that are in common. For example, a memory bus shares capacity in common with various memories requiring transfer. While numerous arbitration schemes have been developed to try and provide fair and efficient allocation of system resources for scheduling problems that involve multiple requesters requesting multiple shared resources, it would be desirable also to have an improved arbitration scheme that provides for higher aggregate usage of the shared resources while still providing a minimum level of fairness.